In order to achieve adequate drive strength and/or ESD protection levels within a MOS-based driver or electrostatic discharge (ESD) protection device, sufficient MOS transistor device width must be provided. Therefore, to create wider structures as well as to meet design rule constraints of pad pitch and maximum active area, devices having multi-finger MOS structures arose in CMOS technologies.
A major concern with regard to multi-finger devices under ESD stress is the possibility of non-uniform triggering and current flow. FIG. 1 is a graphical representation illustrating snapback current/voltage (I/V) curves 110, 120 for triggering multi-finger devices. The graphical representation 100 has an ordinate 102 representing current and an abscissa 104 representing voltage.
The I/V curve 110 represents an I/V curve for a conventional multi-finger device. In order to ensure uniform turn-on of the multi-finger structures, a value at the second breakdown voltage Vt2 must exceed a first breakdown or triggering voltage Vt1 of the parasitic bipolar transistor, i.e., the voltage at the onset of snapback. An initially triggered finger can avoid damage due to a too high current load when adjacent parts of the multi-finger device are also activated into low resistive ESD conduction (i.e., snapback). To achieve the well-known “uniformity condition” Vt1<Vt2, either the triggering voltage Vt1 must be reduced or the second breakdown voltage Vt2 must be increased or both.
Adding ballasting resistance is a common technique used for increasing Vt2. Creating an enlarged drain/source contact-to-gate-spacing by applying a silicide-block technique effectively increases the resistive ballasting in each finger. The considerable drawbacks of this common method lies in the significantly increased area of drivers and ESD protection elements on the integrated circuit substrate, as well as a reduced ESD/drive capability and speed due to much higher parasitic drain load capacitance and larger (dynamic) on-resistance.
To reduce the voltage gap between a lowered Vt1 and Vhold, gate- and/or bulk-coupling techniques can be applied. The smaller the value of Vt1, the less susceptible the structure is for non-uniform triggering. Thus, a lower amount of finger ballast resistance is sufficient to achieve the uniformity condition, as well as having numerous advantages such as smaller area, improved drive performance, and enhanced ESD capabilities. The difficulty of this technique is to derive a suitable bias signal from the ESD transient. Ideally, the bias element/circuit should start to operate at or below the holding voltage, such that snapback, and thus the multi-finger triggering issues, are entirely eliminated. Static (e.g., zener trigger) as well as transient (e.g., RC trigger) gate-/bulk-biasing techniques were used in the past to design as close as possible to this target.
A major downside of transient trigger techniques (such as an RC gate-coupling technique), and in particular with regard to RF applications, is the relatively large additional capacitance load that is introduced at the input/output (I/O) pins. Such additional capacitance load drastically deteriorates normal operation speed. In addition, the implementation of proper RC timing circuits for dynamic biasing (on and off) is very difficult, and at times, cannot be achieved within the limits of the target process technology.
The design challenge of static triggering techniques that reduce Vt1 is finding and harnessing an appropriate breakdown voltage available in advanced technologies (e.g., sub-0.25 micron technology). The doping levels of lightly doped drain (LDD) diffusions in advanced sub-0.25 micron technologies, typically are such that non-leaky zener diodes cannot be realized.
Therefore, there is a need in the art for a method and apparatus for lowering the breakdown voltage Vt1.